1. Field of the Invention
The invention relates to integrated circuit memories and, more specifically, to a method and apparatus for conditioning bit lines in random access memory ("RAM") blocks.
2. Art Background
Random access memories (RAM) are common devices used in computers and many other digital systems. RAM memories typically comprise an array of rows (word lines) and columns, which further comprise bit lines and bit line inverses. Each memory cell (or bit) in the RAM is coupled across a bit line and a bit line inverse. The respective values on the bit line and bit line inverse determine what value will be written to a memory cell in a write operation, or what value will be read from a memory cell in a read operation. A memory cell is accessed by enabling the word line associated with that cell.
Before a memory cell is accessed, for both read and write operations, both the bit line and the bit line inverse of the column of the memory cell being accessed must be pulled high. Also, the voltage across the bit line and the bit line inverse must be equalized. In the prior art, two driver transistors pull the bit line and bit line inverse high and one transistor equalizes the voltage on the bit line and bit line inverse. The gates of all three transistors are provided with a precharge/equalization signal to pull the bit line and bit line inverse high and equalize the voltage between the bit line and bit line inverse. After the bit line and bit line inverse are pulled high and equalized, the memory cell is accessed through its associated word line. Since the driver transistors are typically off, two additional static load transistors are required.
The prior art circuit results in various inefficiencies. First, the two additional transistors increase the size of the RAM. Further, the bit line and bit line inverse are loaded with these two static load transistors and the two driver transistors when the memory cell is accessed. The loading of the bit line and bit line inverse increases the amount of time required to change the value over the bit line and bit line inverse, and thus increases the time required for a read or a write to a memory cell.
The present invention overcomes the limitations of the prior art by providing a bit line conditioning circuit that allows for faster read and write operations and does not require the two static load transistors, thereby decreasing the size of the RAM relative to the prior art.